Dr.Sudhansu Sekhar Nayak, M.Sc(Physics), MCA, Ph.D
Dean(Research and Development)
(1) Lecturer in Physics (Govt. of Orissa) (From 22.2.1975 to 9.7.1990)
(2) Senior Lecturer in Physics (Govt. of Orissa)(From 10.7.1990- 10.7.1998)
(4) Reader in Physics (Govt. of Orissa) (From 10.7.1998 – 30.11.2009)
(5) Professor in Physics and Dean (R&D) Centurion University from 1.12.2009
(6) Preparing students for competitive examinations for last 35 years.
(1) Principal in charge of SKCG(Auto) College
(2) Principal, JITM Junior Science College from 1.12.2009-continuing
(1) 20 years in the field of Digital Signal Processing and Computer Science.
List of Publications:
1. “High Throughput VLSI Implementation of Discrete Orthogonal Transforms Using Bit-Level Vector-Matrix Multiplier” – IEEE Trans. on Circuits & Systems –II: Analog and Digital Signal Processing, Vol. 46, No. 5, pp. 655 – 658, May 1999.
2. “3-Dimensional Systolic Architecture for Parallel VLSI Implementation of the Discrete Cosine Transform” – IEE Proc. – Circuits, Devices, and Systems, Vol. 143, No. 5, pp. 255 – 258, October 1996
3. “Efficient Systolic Architecture for Implementation of 2-D Discrete Cosine Transform”– IETE Journal of Research, Vol. 47, No. 3 & 4, pp 173 – 178, May – August 2001.
4. “Bit-Level Systolic Implementation of Discrete Orthogonal Transforms” – Signal Processing (Elsevier) 81(2001) pp. 2437 – 2443.
5. “Bit-Level Systolic Implementation of 1-D and 2-D Discrete Wavelet Transform”- IEE Proc. – Circuits, Devices, and Systems, Vol. 152, No. 1, pp. 25 – 32, February 2005
6. “New Perspectives of Soft Computing and Fourier Transform in Industrial Applications” – International Journal of Computer Science and System Analysis, Vol. 2(1), pp.79-86, January-June 2008.
7. “Systolic Architecture for Implementation of 2-D Discrete Sine Transform” – Elsevier, Procedia Engineering 30(2012), pp. 441-448.
8. “Bit-level implementation of discrete Fourier transform” –International Journal of Computer Science and Engineering Systems, Vol.5, No.1/2, (Jan./April),2011.
9. “Perspectives of Bio-informatics and Fourier Transforms in Industrial Applications”, International Journal of Bio-informatics.
10. “Two’s Complement Fast Serial – Parallel Multipliers based on Zero- MSB- Of – Multiplier Scheme" under review (IETE)
1. “Bit-Level Systolic Implementation of Discrete Wavelet Transform” Accepted by IASTED International Conference SPPRA 2003, Rhodes, Greece.
2. “3-Dimensional Systolic Architecture for Parallel VLSI Implementation of the Discrete Sine Transform” Accepted by IASTED International Conference, SIIP 2003, Honolulu, Hawaii, USA.
3. “VLSI Architectures for 1-D Lifting Discrete Wavelet Transform”, Accepted by IASTED International Conference VIIP 2003, Benamaldena, Spain.
4. “Systolic Implementation of Discrete Wavelet Transform”, Accepted by Sixth International Conference on Information Technology, CIT -2003, Bhubaneswar, India.
5. “Efficient Implementation of Discrete Orthogonal Transforms for Real Valued Data using a Serial-Parallel Vector Matrix Multiplier”, IIT Kharagpur, June-2004.
6. “Efficient Implementation of Montgomery's Modular Multiplication Algorithm” Accepted byNational Workshop on Cryptology, 2005, Shimoga, Karnataka.
7. “Hybrid Intelligence and Multi resolution Analysis in Industrial Applications”, NSACT – 2007, Rourkela.
8. “A Review of Bioinformatics and Multi resolution Analysis in Industrial Applications ”, MB –07, Jan. 2007, RRL, Bhubaneswar.
9. “Soft Computing and Wavelet in Industrial Applications”, TECHNOBUZZ – 2007, Maharashtra.
10. “A Review of Soft Computing and Multi Resolution Analysis in Industrial Applications”, 21NCCE2007, IE (India), Bhubaneswar.
11. ”Recursive Algorithm and Systolic Architecture for the Discrete Sine Transform”SPRTOS-2011,Kanpur.
12. ”Realisation of One Dimensional DST/IDST using Cyclic Convolution”, NCVESCOM 2011, Paiyanoor, TamilNadu.
13. ”A New Algorithm to Compute the Discrete Cosine Transform.”NCCSN-2008,Guna,MP.
14. ”Algorithm for Computation of Eight-Point One-Dimensional Discrete Sine Transform with Reduced Number of Operations” NCCSN-2008,Guna,MP.
15. “ Hardware – Supportor Interconnect Concurrent Transputer Based Multiprocessor Systems ”, 4th International Joint Conference on Information and Communication Technology, IJcICT – 2012, Bhubaneswar.
16. “Bit-Level Systolic Architecture for a Matrix-Matrix Multiplier”, ICEEE 2011, Nagpur.
17. “4-Bit Serial–Parallel Multiplier and Bit-Level Systolic Architecture for Implementation of Discrete Orthogonal Transforms ”, 4th International Conference on Recent trends in Computing, Communication and Information Technologies, VIT University, Vellore.
Title of paper and name of the author(s) Date For whom reviewed
1.“Properties , Applications and VLSI Iterative 20-6-1998 IEE , London , U.K
Architecture for Unified Complex Hadamard
Transforms” B.J.Falkowski and Susanto Rahardja ,
Centre for Signal Processing , School of Electrical
and Electronic Engineering, Nanyang Techn-
ological University ,Singapore.
2.“A New Distributed Arithmetic Algorithm 10-9-1998 IEE, London , U.K
and its Application to IDCT ” Tian - Sheuan
Chang, Chingson Chen and Chen-Wei Jen ,
Dept. of Electronics Engineering , National
Chiao Tung University, Taiwan.
3.“Fast Implementations of Montgomery’s 20-7-2002 IEE , London , U.K.
Modular multiplication algorithm”,
P.V.Ananda Mohan, Core R&D,I.T.I Limit-
ed , Bangalore , India.
4.“Some Efficient VLSI Architectures for 1-D 05-2-2003 IEE, London, U.K
Lifting Discrete Wavelet Transform”
Pei -Yin Chen , Department of Electronic
Engineering , Tainan County, Taiwan .
5.“The Multiresolution Toolkit : Progressive 16-5-2003 3rd
Access for Regular Gridded Data” John Clyne Conference, VIIP, Scintific Computing Division National Center 2003 Spain
for Atmospheric Research Boulder ,USA
6.“Design of First Bit-Parallel Finite Field 20-6-2003 3rd IASTED Multipliers in GF( 2m
Hua Li, Department of Mathematics International Conference,
and.Computer Science, University of Lethbridge VIIP 2003 Spain
Canada andChang N Zhang , Department of
Computer Science, University of Regina , Canada
7.“A New Distributed Arithmetic Realization 2-11-2003 IEE, London, U.K
of Cyclic Convolution and Its DFT
Application”.H.C. Chen and C.W. Jen
Department of Electronics Engineering
and Institute of Electronics, National Chiao
Tung University , Taiwan and J.I.Guo
Department of Computer Science and
Information Engineering, National Chung
Cheng University , Chia , Taiwan
8.“Wavelet Analysis Method for Fault 13-11-2003 IEE, London, U.K
Diagnosis of Analog Circuits”. Yigang
Hc, Yanghong Tan, College of Electrical
& Information Engineering, Hunan
University, Changsa, P.R China and
Yichuang Sun, Department of Electronic,
Communication and Electrical Engineering,
University of Hertfordshire, United Kingdom
9. “A Pipeline, Memory Efficient and 20-06 –2004 IEE, London, UK
Programmable Architecture for the
2-D Discrete Wavelet Transformation
using Lifting Scheme”, Sara Bolouki
and Omid Fatami, Department of
Electronic and Computer Engineering,
University of Teheran, Iran.
1. Biography has been published in “Who’s Who in the World” published by MARQUIS Who’s Who USA.
2. Biography has also has been published in “Outstanding People of the 20th Century” by The International Biographical Center of Cambridge, England.
No. of PhDs awarded under my guidance: 3
Name of the Thesis:
(i) “Efficient Algorithms and VLSI Implementation of Discrete Fourier Transform” (Ph.D in Computer Science)
(ii) “Novel Algorithms and Architectures for Efficient VLSI Implementation of the Discrete Sine Transform” (Ph.D in Physics)
(iii) “Novel Algorithms and Unified Architectures for VLSI Implementation of Discrete Cosine and Sine Transforms.”(Ph.D in Physics)
No. of PhD scholars under my guidance: 6
Evaluation of PhD Thesis 3
Minor Research Work of UGC: 1
Number of UGC Sponsored Refresher Course Programme participated: 2
Number of M.Tech.Projects guided: 6
A Permanent Reviewer of IEEE